`timescale 1ns / 100ps

module led_demo_tb;

parameter SYSCLK_PERIOD = 10;

reg SYSCLK, SYSRESET_N;

initial begin
    SYSCLK = 0;
    SYSRESET_N = 0;
end

initial begin            
    $dumpfile("output/led_demo_tb.vcd");        //生成的vcd文件名称
    $dumpvars(0, led_demo_tb);    //tb模块名称
end

initial begin
    #SYSCLK_PERIOD SYSRESET_N = 1;
	#1000 $stop;
end

always @(*) begin
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= ~SYSCLK; // 一定要用非阻塞赋值
end

led_demo led_demo_inst0 (
    // Inputs
    .rst_n(SYSRESET_N),
    .clk(SYSCLK),

    // Outputs
    .led(led)
);

endmodule